The present invention relates to output circuits for level conversion from the logic level of a complementary metal-oxide-semiconductor (CMOS) circuit to the logic level of an emitter-coupled logic (ECL) circuit.
Japanese Patent Publication No. 7-70983 shows an output circuit which performs level conversion from the CMOS circuit level to the ECL circuit level. As shown in FIG. 7, this circuit comprises a CMOS inverter 31 including PMOS and NMOS transistors 31a and 31b, PMOS and NMOS transistor 32 and 33 with the gates thereof connected to the output of the CMOS inverter 31, a bipolar transistor 37 as an emitter follower, which has the base connected to the drain signal terminal of the two MOS transistors 32 and 33, the collector connected to a highest potential VCC and the emitter connected to a resistor 30 and also to an output terminal 38, an output resistor 36 connected between the highest potential VCC and the base signal terminal 39 of the bipolar transistor 37, a current source 34 connected to the source of the NMOS transistor 33, and a voltage source 35 for providing a potential VS to the current source 34.
The current source 34, as shown in FIG. 8, includes an operational amplifier 40, an NMOS transistor 41 for receiving at the gate thereof the output of the operational amplifier 40, a resistor 42 connected to the source of the NMOS transistor 41, and current mirrors 43 and 44 including PMOS transistors 43a and 43b, and NMOS transistors 44a and 44b, respectively. The operational amplifier 40 has the non-inverted input terminal driven by the voltage source 35 and the inverted input terminal connected to the source of the NMOS transistor 41. In the current source 34, the NMOS transistor 41 is held substantially at the same source potential as the potential VS provided by the voltage source 35 owing to a high open-loop gain of the operational amplifier 40. The current in the resistor 42 is thus given by the ratio (VS-VSS)/R42 between the resistance R42 of the resistor 42 and the voltage VS-VSS. This current is reflected by the current mirror 43 and then reflected by the current mirror 44 to become a current into the current source 34.
In the output circuit shown in FIG. 7, whether the PMOS and NMOS transistors 32 and 33 are selectively turned on or off, determines whether the current of the current source 34 noted above flows through the output resistor 36 or not, which in turn determines whether a high or a low ECL level is provided to the output terminal 38. When it is designed that a voltage drop of 1 V, for instance, is produced across the output resistor 36 by a current caused therethrough, a low ECL level of -1.8 V is provided to the output terminal 38 by the base-emitter voltage across the output bipolar transistor 37. The voltage drop across the output resistor 36 is determined by the supply voltage VS of the voltage source 35 and the resistance ratio between the resistors 36 and 42. The voltage drop thus is not affected by absolute fluctuations of the resistances of the resistors in manufacture (fluctuations of resistances on the same chip being called relative fluctuations, which are less than the absolute fluctuations). This means that the output level is not affected by the absolute fluctuations of the resistances.
The above prior art output circuit has the following problems. A first problem is that the current source of the output circuit occupies a very large area. This is so because the current circuit includes a large number of elements, i.e., four MOS transistors, an operational amplifier and a resistor. A second problem is that the output level fluctuates greatly due to MOS transistor gate size fluctuations. This is so because the output circuit uses the MOS transistor current mirrors. The fluctuations can be greatly reduced by extremely increasing the MOS transistor gate width. By so doing, however, the area of the current source is increased.
The above problems will be discussed in greater details. Regarding the width and length of the gate of the MOS transistors of the current source 34, according to the above patent publication it is possible to set the width and length of the gate of the PMOS transistors 43a and 43b to 50 .mu.m and 5 .mu.m, respectively, set those of the gate of the NOMS transistor 44a to 10 .mu.m and 2 .mu.m, respectively, and set those of the gate of the NMOS transistor 44b to 100 .mu.m and 2 .mu.m, respectively. Obviously, the current source which includes many elements, i.e., the four transistors and a further transistor 41 as well as the resistor 42 and the operational amplifier 40 (an operational amplifier shown in, for instance, P. R. Gray and R. G. Mayer, translated by Yuzuru Nagata,"Analog Integrated Circuit Design Techniques, Part II", page 227, FIG. 12.38, including twelve MOS transistors and three bias current sources), occupies a large area.
Reducing the MOS transistor gate size to reduce the occupied area, leads to a problem of ECL output level fluctuations due to gate size fluctuations in manufacture, which will now be discussed. When the gate length is set to a minimum of 0.5 .mu.m while maintaining the ratio between the width and the length of the gate, the width and the length of the gate of the PMOS and NMOS transistors 43a and 43b are 5 .mu.m and 0.5 .mu.m, respectively, those of the gate of the NMOS transistor 44a are 2.5 .mu.m and 0.5 .mu.m, respectively, and those of the gate of the NMOS transistor 44b are 25 .mu.m and 0.5 .mu.m, respectively. When the reference gate width error in a lot manufacture process is set to 10% of the minimum width, i.e., 0.05 .mu.m, fluctuations are produced in the current mirror 44 in FIG. 8. The center value of the gate width ratio between the transistors 44a and 44b is 10. When a gate width error of 0.05 .mu.m is produced, the gate widths of the NMOS transistors 44a and 44b are changed to 2.55 .mu.m and 25.05 .mu.m, respectively, changing the gate width ratio to 25.05/2.55=9.82. This value is a 2% deviation from the center value.
This deviation corresponds to a reference current deviation from the case where the gate width has the center value. In this case, when the output level is"low", a voltage drop of 1 V is produced across the output resistor 36, and 2% of this voltage, i.e., 20 V, is the reference deviation of the output voltage. When it is estimated that three times the reference deviation is the maximum deviation that actually occurs, the output level deviation is .+-.60 V, width 120 V. Since the rated ECL output level deviation width is 220 V, the fact that more than one half the rated deviation width of 120 Mv is introduced by the above gate width error, leads to such undesired results as cost increase due to yield reduction or the like in the actual construction.